This invention relates to phase-locked loop circuitry. More particularly the invention relates to a data detection circuit including a phase-locked loop circuit that uses a dual-output multivibrator to phase align clock and data pulses.
Previous phase-locked data detector circuits use a monostable multivibrator circuit having a pulse width equal to the pulse width of the voltage-controlled oscillator. With pulse widths equal, detection of a "1" in the data input occurs on the rising edge of the voltage-controlled oscillator pulse, while phase detection takes place on the falling edge. In order to maintain small steady-state phase error, prior art circuits require that the pulse width of the monostable multivibrator be tuned dynamically to match the pulse width of the voltage-controlled oscillator as the oscillator changes frequency with a varying control voltage input. Practical implementations of the prior art require that both the nominal frequency of the voltage-controlled oscillator and the pulse width of the monostable multivibrator be carefully controlled or adjusted at time of manufacture in order to maintain a small steady-state phase error.
For many of the prior art circuits, the correction logic used creates a "dead band" at near zero phase error. This occurs unless the difference in phase between the single-shot multivibrator pulse and the clock pulse exceeds the set-up time of the correction logic. During such dead-band time, no correction signal is generated. Consequently, the circuits exhibit an inherent jitter as utilized in phase-locked data detectors.